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Veristand cRIO and XNET 986x

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Hello All,

 

I find some KB and tutos which explain that cRIO XNET CAN Modules 986x are supported by Veristand.

 

I use this tutorial to configure my Veristand project : http://www.ni.com/tutorial/14706/en/

 

However I encounter a problem. When using 986x it is said that I hace to select the bitfile I just compiled in the 986x Configuration page.

 

How should I develop a LV FPGA VI that manage 986x for Veristand ? Is there any kind of example or template to respect ? 

 

Really I don't uderstand how my LV FPGA needs to look like....

 

In this tuto it is just said that I have to create a blank LV FPGA VI ....

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Yep just a blank VI will do
Stephen B
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So just to be sure :

 

I have to compile a blank LV FPGA VI and it's this "blank" bitfile which will be loaded by VS ? And will allow me to use my cRIO 986x natively under VS ? How do all the mechanism of DMA are implemented ?

 

Really, I don't understand very well how it will work 🙂 ...

Could explain to me the mechanism under the hood ?

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Solution
Accepted by topic author SmileBoB

The trick is in the settings of the project. The module communicates in the background aka scan engine. So compilation of empty vi will add this underlying mechanism.

If you go to Help - Find Examples and search for 9862, there is an example project called NI-XNET CAN CompactRIO.lvproj. You can use it as a starting point.

 

C:\Program Files (x86)\National Instruments\LabVIEW 2013\examples\nixnet\projects\NI-XNET CAN CompactRIO\NI-XNET CAN CompactRIO.lvproj

 

Jiri

CLA, CTA, CLED

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