VeriStand Error 15 from .fpgaconfig

[joedowdle]

I got Error 15 when I tried to use a custom .fpgaconfig file and I can't figure out what the problem is.  I am in the process of moving testing to using VeriStand and RT/FPGA so I am still learning.  I'm not sure where to start with this error and nothing came up when I did a quick search.  I included a screen shot of the error box.

Thanks.

[Andrew_B]

Hello Joe,

FPGA code written to work with NI VeriStand must follow a specific template to:

• Import into a VeriStand System Definition File 
• Interface with the VeriStand Execution Engine

The Creating a Custom FPGA Bitfile topic in the VeriStand Help files includes several guidelines for writing and modifying FPGA code. Based on your attached error code, several relevant guidelines are:

• Do not modify, remove, or rename any block diagram objects in the gray areas of the sample FPGA VI.
• Do not use the following control/indicator names: Loop Rate (usec), Write to RTSI, Use External Timing, Reset, Start, or Generate IRQ.
  

I recommend opening a sample VeriStand FPGA VI and checking if your FPGA VI still contains all the same front panel Configuration controls (especially the "Start" control). Also, make sure no other front panel controls are named "Start".

If you cannot find or have modified the sample VeriStand FPGA projects, I have attached the projects (Templates.zip) and a JPG of the relevant front panel section.

If this does not resolve the problem, I recommend checking the <Parameters> sections of your fpgaconfig file. Referencing the Creating a Custom FPGA Configuration File topic in the VeriStand Help, you will need to either:

1. Add a <ControlName> item referencing a front panel control that is not named "Start" to a section that contains <Name>Start</Name>
2. Modify an existing <ControlName>Start</ControlName> item to reference a front panel control that is not named "Start"

Regards,

Andrew Brown