06-21-2022 05:14 AM
Hello I want to use the FPGA in Veristand. I followed this link to do it :
However when I import the file LABView real-time in Veristand, It works, but I don't have the user variable that I used in LABview.
Maybe the probleme is I have Labview 32 bits 2021 and Veristand 64 bits 2021 and I found that Veristand is compatible only with labview 64 bits. But I use a compactRIO that is only compatible with Labview 32 bits? Maybe somone can help me.
Thank your for your answers.
Solved! Go to Solution.
06-21-2022 10:56 AM
You should have no problem at all using LabVIEW 2021 FPGA 32-bit to make a bitfile, and then using VeriStand 2021 and the Scan Engine and EtherCAT Custom Device to interface with that, deploy to RT, and execute against this. Including accessing those user variables.
Can you provide more information? i.e. When following the steps in the KB -- at what point does your experience stop working and looking like the screenshots shown there?
best of luck,
06-22-2022 02:44 AM
Firstly Thank you for your answer.
Okay I will show you how I import the Labview FPGA File.
1. I add the cRIO in Labview, discover the FPGA, and put the module 9205 in it.
After I create a FPGA Targer VI.
I did a little easy programm to see if it works.
The one thing that I'm not sure, if I have to put the while loop?
And the second, I use a NI-9205 without the D-sub
And in the labview FPGA it is the input of the 9205 with the sub.
So I found this :
And I said to do ACH0 of my 9205 I have to do :Al0 - Al8.
After this I Clicked on the run
The compile started, and 15 m after it was done.
I went on veristand in configure COntroller -> custome devices - scan engine - local chassis - user variables and I add the fille that was juste created.
So that it, tank you for your help.
(I have another problem it's when I did this all thing, after the veristand can't anymore run
06-24-2022 08:53 AM
I suggest first establishing that you have all of the Hardware set up correctly and VeriStand, Scan Engine and EtherCAT Custom Device can discover your modules -- and don't jump straight into FPGA customization on that device until you establish this is working.
Are you able to achieve and outcome like this? where you become "Connected" and can read some I/O data back from one of your C-Series modules. [this does not require FPGA Bitfile compilation at all]
Shown here is my cRIO-9033 with an NI 9213 C-series module in Slot 2. I used NI MAX to get the cRIO configured and firmware updated and software installed. Then I used VeriStand System Explorer to add the Custom Device and then Discover the modules. Then deployed, went back to VeriStand and dragged one of the module channels to my screen.
06-24-2022 08:59 AM - edited 06-24-2022 08:59 AM
Yes I have already done this part (veristand, scan engine...), I did a little temperature control and it works with the inputs and outputs. And so now I want to measure a speed with the same program and it's why I go to labview fpga.
06-30-2022 04:14 PM
One thing that can cause that TCP error is related to VeriStand deployment getting hung up trying to ask for a WebDAV password on the RT target -- or at least today after setting a password on my cRIO I started occasionally seeing this user/pass prompt from VeriStand.
Try rebooting the RT target, restarting the VeriStand editor then doing a fresh deploy.
Odds are you may find this prompt pop up,
if you do and set the user/pass correctly -- your deploy should work fine. I've seen the TCP error when this dialog should have popped up but didn't for whatever reason (issues with local networking configuration? unclear)
This user/pass prompt has a troubled history, can read more about it here:
06-30-2022 06:27 PM - edited 06-30-2022 06:28 PM
Actually I have one other idea, perhaps more likely in your case, regarding the cause of the TCP error that may be what is going on here.
When you connect to a cRIO using LabVIEW FPGA, LabVIEW will show you a dialog that says that there's a VeriStand application running on the cRIO and it must be shut down in order to proceed with the deployment associated with the VI Run button action. This enables LabVIEW RT/FPGA control of the cRIO, however it will cause all subsequent attempts of VeriStand to connect with that same TCP error.
To get VeriStand restarted on the cRIO and ready for VeriStand deployment, there's a handy command to restart the engine on the RT target:
once that command completes, the RT target will be VeriStand ready again, and now future deploys should work without a TCP error.