09-15-2014 06:41 AM
Hello,
I am new to Veristand so I am trying do to some rather simple tassk.
I have 2014 Veristand and I am using a cDAQ 9174 with a 9402 module.
I have configured this card in MAX I have been able to read an frequency signal by creating an MX task in MAX. I am aware that my requested channel of CI0 has to have my counter pickup plugged into CI1 to read a signal and in MAX it work fine.
WHen I try to read this signal (CI1) in veristand I get some junk value.
When i try to read from CI0 i get a value but it updates very slowly and is not the same value as I am able to read in MAX.
When I reconfigure the channel from a frequency type channel to a counter in the veristand system explorer the signal counts up so I know my hardware is active.
Any ideas on how to configure this channel
Thanks
09-16-2014 05:07 PM
Hello Tim,
It's my understanding that VeriStand only natively uses a single counter Count Edges frequency acquisition. Have you tried connecting your input frequency to a single counter source and reading that channel?
What is your minimum frequency currently set to? You should try leaving this at 1 Hz if you may have changed it.
Let us know if this helps!
Andy C.
Applications Engineer
National Instruments
09-17-2014 06:06 AM
Hey Andy
I am not sure if I have connected to a single counter. as I mentioned in the previous post I am using NI 9402 cDAQ DIO LVTTL module do acquire my frequency input.
My min frequency was set to 0.01 and my MAx was set to 1000 Hz in the channel settings as shown below
I did change this min frequency to 1000 hz but it didn't help.
09-17-2014 02:35 PM
Hey Tim,
You should try a minimum frequency of 1 Hz. The frequency is calculated using the VeriStand control loop time-base as a reference, and I'm not sure if this will cause problems for frequencies below 1 Hz.
Let us know if that changes anything!
Cheers,
Andy
09-18-2014 06:35 AM
I tried a frequency minimum of 1 Hz which really didn't change anything. The update speed is still slow. It seems any graphs or data are only updated at 1 Hz.
09-18-2014 07:23 AM
Check your loop durations and loop late counters (System Variables). Perhaps the DAQ calls within the loops are waiting for edges to occur which is then slowing down VeriStand's processing loop(s).
09-18-2014 11:34 AM
Once again thanks for the help but my experience with veristand is limited. WHere do I check for these systems variables?
09-18-2014 11:52 AM
Within the workspace, select Tools: Channel Data Viewer. That tool can display any channel in VeriStand so within there you should be able to browse to System Channels. Some System Channels provide some feedback as to how your system is running. Two important ones are HP and LP Loop Duration as they tell you how fast your loops are running. If they are close or exceed your desired rate (e.g. 1,000,000 nsec HP Loop Duration and you are trying to run at 10 khz (100,000 nsec) then you have something wrong or too much going on to achieve that rate...
09-19-2014 06:58 AM
Thanks for the input.
The number I am seeing are whay above what you have described.
The test that I will be trying to run requires that my controller acquires and commands data at a rate of 1000 Hz perhaps this is causing the problem?
09-19-2014 07:12 AM
Your large HP Late Count means the main control loop is not completing within the timeframe you established (e.g. 1 msec ). This matches with the HP Loop Duration which shows that loop is taking over 1.1 msec to complete. I would start removing items from the system definition (you could start with the prime suspect, your RPM input). If you HP Loop Duration and Late Count come in line, then you know it is just your RPM input that is causing the problem. Assuming it is the RPM input, I would apply differenty frequencies to that input and graph the HP Loop Duration to see if there is any correlation between HP Loop Duration and input frequency.