I try to import a Labview FPGA model for Veristand. However I have a problem with the "user variables". I cheched on the net and it said that maybe I have the compilation in another language than english. However I have labview in egnlish and veristand in english.
Or maybe I " If you have the UDV container with different name when creating a bitfile from LabVIEW, VeriStand will throw error 537707 when the bitfile is deployed" it is what I found on the net however I don't understand very much this sentence.
Thank you for your help. I put some photos to show you.