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What is the maximum rise time for the EXT CLK input on a VXI-MXI-2 Slot 0 Controller?

We're using an external clock into a VXI-MXI-2 Slot 0 controller.  The signal has a pretty fast edge and is producing a lot of harmonics on the chassis ground.  We are trying to slow down the edge to reduce harmonic content, but we're not sure how slow of an edge the input can handle. 
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Hi there,

I checked in the VXI-MXI-2 User Manual, and I could only find information for frequency range (10 Mhz).  I did find another document that is saying the MXI bus transceivers typically generate signals with rise times of 9ns.  What kind of rise time are you looking at?


Adam W
Applications Engineering
National Instruments

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We started with a <3nSec rise time. Right now, we've slowed it down to about 8nSec and its still too noisy.  Doesn't look like we should go much slower if 9nSec is correct.  Any other ideas on how to reduce harmonics on the Chassis Ground from the 10MHz?
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How are you measuring the harmonic noise on the chassis ground?
Also if you stop producing the external clock does that eliminate the harmonics on the chassis ground?


John E.
Applications Engineering
National Instruments
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