Real-Time Measurement and Control

Showing results for 
Search instead for 
Did you mean: 

Why my system slows down with thermocouple module used

I am working on close loop control based on accelerometers thermocouple  and sine generation.

So far I have figured out how to control sine generator and thermocouple module separately.

When I include thermocouple module code to generator code it slows sampling rate to 4.8Hz or similar to it.

I have tried to put thermocouple code part into different places but nothing worked.

Could somebody take a look into my code and comment it?

I will need to add accelerometer code bit later on so that will need sorting out.

Download All
0 Kudos
Message 1 of 4

Hi Sergey,

An FPGA While will run as fast as it can, the things that slow the loop down are any timing waits that you code, and the speed of any modules that are accessed in the loop.

The cRIO NI 9211 has a response of  of only 70 ms per channel andyou are effectively reading 3 channel, Channel 1, Autozero, and CJC, this gives you a total time of 210ms or 4.76 HZ.  The Loop Timer that you haveput into the code will be totally ignored unless it has a value greater than 210ms. 


To get the speed that you require you simply need to recode so that the slow modules are in one loop and the fast modules are in another loop.  FPGA will carry out true parrallel operation on the two loops and each loop will operate as fast as it can.


You might also consider whether you wish to use several while loops, and DMA to transfer data rapidly where you have a lot of data to shift from the FPGA to the RT.




Message 2 of 4

Thanks Stephen,

I'll take a look into code.

The question  have got for separate while loop:

I create separate while loop put FPGA I/O node into it for thermocouples and what should I do to the FPGA error out?

Do I need to use 2 different FPGA error out or merge errors into one outside the while loops?

0 Kudos
Message 3 of 4

Hi Sergey,

What you do with the FPGA error depends entirely upon whether you will apply different actions to the errors, and the available space that you have on the FPGA.

If you need specific actions then deal with the errors individually, merging the errors will only be useful if there is some way of communicating between the FPGA loops.

In short it entirely depends upon what you want to do with the errors. 



Message 4 of 4