06-23-2023 10:16 AM
As I understand it, reading an analog input on an FPGA module, such as the PXIe-7857, is limited by the maximum sample rate of the device (1 MS/s for the PXIe-7857). Would reading a digital input be limited by the same maximum sample rate, or can a digital input be effectively read at the top-level clock rate for the VI (could be 80 MHz for the PXIe-7857)? I'm guessing the "maximum sample rate" is a limitation of the ADC and only applies to the analog inputs...
Solved! Go to Solution.
06-23-2023 11:31 AM
@rms0 wrote:
As I understand it, reading an analog input on an FPGA module, such as the PXIe-7857, is limited by the maximum sample rate of the device (1 MS/s for the PXIe-7857). Would reading a digital input be limited by the same maximum sample rate, or can a digital input be effectively read at the top-level clock rate for the VI (could be 80 MHz for the PXIe-7857)? I'm guessing the "maximum sample rate" is a limitation of the ADC and only applies to the analog inputs...
Yes, DIO has a maximum frequency of 10MHz or 80MHz. The information is available in the NI PXIe-7857R Specifications
06-23-2023 12:30 PM
Ah, I missed that table. Thanks for the speedy solution, ZYOng!