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HDL compiler fails on IP integration

Good morning everybody,

 

hopefully to post in the right community section, I am experiencing troubles when trying to generate an IP block from an imported VHDL code snippet.

 

I am working on a NI PXIe-1078 integrating a NI PXIe 7962R (FPGA Xilinx Virtex-5 SX50T), Microsoft Windows 7 64-bit with LabView 2017 32-bit. On the IP generation wizard, I successfully follow the procedure, however on the last step (6 of 6) I receive the following error feedback on the console:

 

Use this page to configure the data type and appearance of each block diagram terminal that represents a VHDL port.

 

ERROR:HDLCompiler:806 - "C:\NIFPGA\iptemp\ipinAF0E4ABB3A564AB9B784C48450C8D7E3\ISE\algorithm.vhd" Line 1: Syntax error near "clk".

ERROR:HDLCompiler:854 - "C:\NIFPGA\iptemp\ipinAF0E4ABB3A564AB9B784C48450C8D7E3\ISE\algorithm.vhd" Line 1: Unit <algorithm> ignored due to previous errors.

ERROR:HDLCompiler:374 - "C:\NIFPGA\iptemp\ipinAF0E4ABB3A564AB9B784C48450C8D7E3\ISE\algorithm.vhd" Line 1: Entity <algorithm> is not yet compiled.

ERROR:HDLCompiler:69 - "C:\NIFPGA\iptemp\ipinAF0E4ABB3A564AB9B784C48450C8D7E3\ISE\algorithm.vhd" Line 1: <natural> is not declared.

ERROR:HDLCompiler:374 - "C:\NIFPGA\iptemp\ipinAF0E4ABB3A564AB9B784C48450C8D7E3\ISE\algorithm.vhd" Line 2: Entity <algorithm> is not yet compiled.

ERROR:HDLCompiler:210 - "C:\NIFPGA\iptemp\ipinAF0E4ABB3A564AB9B784C48450C8D7E3\ISE\algorithm.vhd" Line 3: Architecture behavioral not found in entity confd315dc6c688041c2aa8a065b17eb4764

ERROR:HDLCompiler:854 - "C:\NIFPGA\iptemp\ipinAF0E4ABB3A564AB9B784C48450C8D7E3\ISE\algorithm.vhd" Line 2: Unit <confd315dc6c688041c2aa8a065b17eb4764> ignored due to previous errors.

Error 1430 occurred at Open/Create/Replace File in MD5Checksum File.vi->niFpgaIPINodeConfPage6.vi

 

Possible reason(s):

 

LabVIEW:  The path is empty or relative. You must use an absolute path.

 

Following the specified path (an temporary self-generated folder, I guess), I find the same snippet and opening it I can easily recognize the error:

 


 clk                                :    in    std_logic := '0'
library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

entity algorithm is
(continue...)

 

In other words, when selecting the generic or I/O ports from the wizard, the temporary file is not correctly generated and thus the compiler cannot proceed.
Moreover, the wizard nor let me to go back or end the procedure as all the buttons of the windows are kept unhighlighted. So if I try to manually modify the generated file, the IP block will not be eventually generated anyway.

Any solution or workaround? Thank you in advance.

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After upgrading to LabVIEW 2016 I experienced the same issue, but strangely with only one VHDL file - I used many. I had to stip the architecture body to a single assignment ( I have only one output port ) to see this message, befor it reported: Error -4701 occured at Error occured during regular expression match.

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After almost a day of trying ( everything ), I found a solution. For me setting the FPGA Family Support to Zynq ( my target device ) resolved the problem. I could redo the error by chosing unlimited again. I'm not sure though if it's the only thing in play I did quite a few things:
-Deleted all "cached" files.

-Opened the project, forced a save and the closed all labview processes.
-Made the whole source uppercase ( i reverted this later )

the rest I don't remember, sorry


 

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