01-25-2022 06:44 AM
I'd like to generate a consistently identical output signal from PXIe-4463 upon reciept of an pxi_trigger.
I can send the trigger and the signal is generated, but the phase has a variation of about 4.8e-6s. Is this the best I can expect?
The PXIe-4463 is configured to generate a sinusoidal signal and the signal is reset such that the phase input is used. The phase is set to 0°. These samples are generated prior to configuring the DAQmx task to start on a digital edge from pxi_trig.
I send the trigger from a digipat event and the PXIe-4463 reacts as expected; generating the signal with a 83 sample delay (I'm using a sample clock of 51200Hz and the manual lists this as the sample delay for this sample rate).
The sample clock of the DAQmx task does not have anything on the source input and I read this as defaulting to "onboard clock". I also think that "onboard clock" means the 10MHz reference clk of the PXIe chassis (PXIe-1085). Am I wrong about that?
I would like to somehow synchronize the PXIe-4463 and the PXIe-6570 so that the generated signal has less than 0.1e-6s variation.
01-25-2022 11:05 AM - edited 01-25-2022 11:06 AM
Maybe you can reduce the jitter but may not up to the 100ns variation you require.
83 sample delay is due to the filter at the front end of the Delta-sigma DAC of 4463. For DSAs the sample clock is always onboard clock due to their oversampled nature and free running. You can configure the PXIe_CLK100 as a reference clock (not the 10MHz on a PXIe chassis).
Triggers sent on PXI_TRIG line are always 100ns wide (1 clock of 10MHz), in addition to this, each instrument has its own delay to process this trigger and react, hence it cannot be faster than 100ns on a PXI_TRIG line.
It is worth trying to make the DSA as the trigger source and let the 6570 react to that trigger instead of the other way around.
What does this 6570 and 4463 connect to, what is the DUT and setup, why do you need the 100ns synchronization?