PXI
FPGA DMA FIFO Data Write
Hi Everyone,
I am currently having some problems writing to a DMA FIFO in my project. I tried to attach the project buit it produced an error code so I have had to resort to using screenshots which are frustratingly mangled!
I am really sorry about the fractured way that I am having to update this message but I wrote a rather long post that refused to upload and I lost all of it so I am going to do it this way to be safe. So, first of all thank you for reading my post - I am new to LabVIEW in general and have no real experience with the software, epsecially not LabVIEW FPGA.
In this project I want to write some data to a DMA FIFO. This project is something of a trial run that I am trying to get to work before I attempt anything more ambitious. The basic idea is to read some data from a host VI down a DMA FIFO, across the FPGA and then back up to the host where it is stored in a text file. In the host VI I want to isolate the two spearate processes so I begin by referencing the VI and then stating the size of each of the buffers.
In this project I want to write some data to a DMA FIFO. This project is something of a trial run that I am trying to get to work before I attempt anything more ambitious. The basic idea is to read some data from a host VI down a DMA FIFO, across the FPGA and then back up to the host where it is stored in a text file. In the host VI I want to isolate the two spearate processes so I begin by referencing the VI and then stating the size of each of the buffers. For the write to FIFO function I want to pass it a series of random numbers which I pass to the block. However despite changing the formats of the data the FIFO buffer accepts it will only allow an array of a particular data type to be passed to the block, I can't directly pass it the value. So outside the while loop I initialise a 1D array and then inside the while loop I insert the randomly generated value into this array and pass the array to the Write block. From there however I then receive no apparent data on the FPGA or from the read block in the other section of the Host VI. Can anyone help me find out how to transmit data to the FIFO in such a way that it actually comes out again opposed to the long string of 0's that I am getting at the moment. Below is the schematic of the FPGA VI
I have tried a number of different things to change this however I haven't suceeded getting it to work - I have a feeling it might be something to do with maybe the clock rate as the FPGA is cycling much faster than the host FPGA, although I have no way to confirm this vague suspicion let alone fix it!
The major issue I see is that you are starting up your FPGA twice. You only need to open the FPGA reference once. You then pass that reference to all of the places that need it. Also make sure that you don't close the reference until everybody is done (use merge errors after your two while loops and then close reference).
