Minimizing power usage

[Mads]

We have a sbRIO-9627 card that we need to reduce the power usage on as much as possible (not just when idle, but that too...). Any tips on how to do that?

Downclocking the CPU is fine, if possible, as we do not need it to be particularly fast.The only peripherals that will be connected to the card is the SD card, the Ethernet port and the serial ports, so anything else could be turned off if possible(?). 

[Call.Me.Wilbur]

A good way to reduce power consumption is to deactivate onboard IO with the Sleep function when the IO is temporarily unsed. Additionally, if some onboard IO is entirely unused you could remove it from the project to prevent that IP from being compiled into the FPGA bitfile at all.

The sleep function also applies to any C Series modules you may be accessing through the RMC connector. The sleep signal can be sent to these modules to save power when the IO is temporarily unused.

Another easy option is to compile your bitfile with the "Optimize Power" implementation strategy. This can be found in the "Xilinx Options" category of the Build Specification settings.

[Mads]

sbRIOs do not have the sleep function...and we are not using any C series modules or RMC either, so I was hoping for other alternatives.

Underclocking is what I assume would be the most power saving option, but anything that can save power is welcome.

[BradM]

I think the best bet you'd have is to get your hands dirty, look at the kernel configuration options available to you (e.g. cpufreq functionality, and the CONFIG_PM kernel configuration option) and keep in mind that power management almost always will decrease system determinism (as well as performance), so you may wish to change the preemptibility of the kernel to match your needs.

Here's Xilinx's documentation on what's needed for Zynq power management. Following that guide (mostly for the config options), I've booted a system that is running at 333MHz, so it is possible. Also note that a non-trivial portion of the SoC power budget is taken by the FPGA fabric, so if you have a busy design in the fabric, the ARM clocking is not going to get you too much.

Note that building your own kernel is not supported by NI, has not been tested extensively, etc. etc., and will not persist over certain software installation actions performed through MAX.