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how do I programmatically determine the number of bits in a fixed point number?

I have a fixed point value of type <+, total number of bits, number of integer bits>

how do I programmatically determine the total number of bits ? I don't see this in the property node menu.

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Message 1 of 8
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Hi art,

 

why do you need this?

Do you want to set the FXP datatype or do you "just" want to know/read/get the number of bits?

 

Anyway: FXP size is set at edit time: why don't you just read the context help when you move the mouse pointer on the FXP wire?

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 2 of 8
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You can use Data Type Parsing pallete or VI hidden in vi.lib:

fixedpoint.png

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Message 3 of 8
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I just want to know the number of bits. Though it would be nice if I could programmatically generate a cast for a fixed point type.

The application is this: I have a collection of fixed point numbers to pass over P2P & DMA fifos. They need to move simultaneously so I'm going to pack them into a U64. I can do it by hand but I want to keep the result generic so I can change the size of any of the inputs without figuring out manually how far to shift-left things as they are packed in or shift-right things as they are unpacked. And to use it elsewhere.

 

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Message 4 of 8
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Thanks PiDi. That did the trick for host-side. Now I need one for the fpga side. When I place this one on the fpga vi it says the vi is non executable. Judging by the error message maybe it has something to do with the presence of error handling. The block diagram is password protected so I can't reproduce it from primitives. Suggestions ?

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Message 5 of 8
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I'm confident that there's no way to do this on the FPGA. Can you show how you would use it there? Do you really need to do this on the FPGA side? I think you'd be better off finding some way to share the information between the FPGA and host, such as by using a type definition that's used on both sides but only interpreted by the host, or by having the host send the numeric representation information to the FPGA.

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Message 6 of 8
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This would still require a recompile so maybe a pre compile tool could be run to determine this?


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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Message 7 of 8
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Hi art,

 

I have a collection of fixed point numbers to pass over P2P & DMA fifos. They need to move simultaneously so I'm going to pack them into a U64.

Usually you do this by creating a kind of "message" in your U64 value.

You could use the upper 16 bits to store information about the kind of data in the remaining (lower) 48 bits.

On the FPGA you know at edit time, which datatypes you want to handle: there might be some voltage signals, some current signals, some boolean ports or some CAN data. Each of them has a certain representation (like [FXP26,5,±], U8 or 2×U32) and you know/decide at edit time how to pack those data into your U64 "message container"…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 8 of 8
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