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fpga dsp, FFT xilinx block

Hi at all,

I'm working on LabVIEW FPGA in DSP environment and I have some questions about the FFT Xilinx block ( Core gen 7.1 ) 

 

My clock is 130Mhz and data run with a clock much smaller ( 1 data every 13 clock cycles )... Data are pushed out from a FIFO and signalled with a Input_Valid signal.

 

Is there any PIN on the FFT block that allows to insert input data only when the Input_Valid signal is asserted ???

( I tried to connect Input_Valid (FIFO) to Clock_Enable (FFT), but does not work because if there is no data the FFT block is in stall... )

 

Second, What is the purpose of the fwd_inv_we signal ???

The manual said : Write enable for FWD_INV (Active High).

Actually I have connected the Input_Valid to fwd_inv_we but seem that does not work!!!

 

To simplify the questions  FFT vi and time diagram have been attachments.

 

Thanks in advance Simone C.

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