I made a VI for an FPGA in a test project and it worked perfectly. It is a code to generate a PWM and my controller is attached to a oscilloscope so I can see directly if it works.
Since the test project was full of other tests I decided to start a new project to start fresh. I exactly copy and pasted the block diagram into the new project, but now it doesn't work anymore. I get no errors, the code compiles and when I run it in simulation mode it gives exactly what is expected. It just doesn't show anything on the oscilloscope anymore. When I switch back to the other file in the other project it works again, so there is nothing wrong with cables or anything.
Did I miss a step when making the new project? What could be wrong? The controller is connected. Thanks in advance!
so there is a problem with your VI and you want us to analyze that problem?
Without looking at the code (and all related properties, kept in the project)?
Do you access FPGA resources inside that VI?
Did you relink those resources, just to make sure the VI uses the correct resources?
See if this works.
This should eventually converge on a small "working" Working Copy.