I still don't understand about Simulate Signal Express VI which I use to generate sine wave adc on myRio. In Simulate Signal Express VI there are samples per second and a number of samples that are related to each other. In my project, I'm trying to set samples per second to 1000 and number of samples to 200 in simulated signal express VI. It worked normally when I set the timed loop period to 200ms, the measured samples per second was 1000 samples and matched what I set earlier.
However, when I set the timed loop period to 100ms, the measured samples per second is 2000 samples and does not match the samples per second setting on the Simulate signal express VI. Is it correct if I assume that to get the desired sampling rate using Simulate signal express VI I only need to care about the number of samples and timed loop period ?
Without even looking at your myRIO Project (which, of course, I cannot do, since you didn't include the entire Project, compressed and sent as a .ZIP file, but only pictures which can't easily be executed and are often "incomplete". I also saw references to the Simulate Signal Express VI (which, itself, generates a signal using some form of internal clock) and a Timed Loop (which has a separate clock) to generate, presumably, each D/A point.
The simple way to generate a sinusoidal signal with the myRIO and the myRIO Software Toolkit is to decide on the rate you want to update your signal. Note that this is the rate that you send signals to the DAC, and is much higher (factor of at least 10) than the frequency of the sinusoid you are generating.
Let's say you want a Sampling Rate (Sf) of 1 kHz. What is your update interval? 1/Sf = dt = 1 msec. Let's say you want to generate a signal f(t) that approximates a Sinusoid of frequency F. For simplicity, I'm going to ignore any Bias or Phase Offset. The formula which can be computed for every value of t is f(t) = sin (2*pi*F*t). How do t vary? The next t = t + dt.
So here's your sinusoid -- Create a Timed Loop with a clock rate of dt. Set a Shift Register in the Loop to the initial t (= 0, for convenience). Inside the loop, compute f(f) using the above formula (note that F is assumed constant, but you could make it vary as a function of time, if you want to get fancier). This computation should take a few microseconds. Output this (single) value to the D/A Channel of your choice using the myRIO Toolkit Express Analog Output VI. Update the value of t in the Shift Register by adding dt.
You might notice that the event you want timed, namely the output to the DAC, does not happen first in the Timed Loop. However, with a little bit of thought, you should be able to do the DAC first, then update things for the next time through the loop. Exercise left for the reader.
But do reply with your attached Project. It will be different from what I'm proposing, as I don't have any direct involvement with the myRIO's FPGA -- I do it with the Express VIs that target the default FPGA routines in the Toolkit.