Time required to read Block RAM in Labview FPGA

[padhu_1]

Hi,

Am using PXI 7820R FPGA board. I have configured block RAM to store and read data. Each location stores 1 Byte Data (8 bit). I need to send data from 7820R (Slave) to my DUT (Master) based on command received from DUT.

I need to read 1 byte data from the location and send it in the SPI as bit-by bit during every clock cycle of SPI.

The once again i need to increment the address location and send in the data same way. My SPI clock period is 1us.

Here i am facing issue in timing to read data from BRAM. Its taking almost 400ns wrt SPI clock. Also it taking almost 200ns to write data in the MISO.

Please suggest me on this issue

[Terry_ALE]

When you configure the BRAM it gives a selection of 1, 2, or 3 cycles.  What did you select?

What is the clock rate of the loop that has the BRAM read?

[padhu_1]

Hi Terry,

Initially read cycle latency was 2 cycle, i have changed it to 1 cycle and tried. But the result is same.

The read BRAM memory happens in a normal while loop. Attached the way its implemented.

onboard clock is 40 MHz and 80MHz clock is derived from it.

[Terry_ALE]

I would consider using a single cycle timed loop to get better control over timing.  A regular loop in LabVIEW does not give a lot of control over timing.