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Starting multiple SCTL with same clock domain

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Hi,

I have question regarding multiple SCTL loops and when they start. You can see in attached snippet that I have multiple VIs that share same integer value. This value is default for timestamp that is inside in every VI with SCTL (Encoder Channel, TMS Gen.). As I use value of timestamp from TMS Gen. in different part of application I need to be sure that Encoder Channel and TMS Gen. has same timestamp. I know that once running these SCTL increase it's own timestamp as others but I am not sure if they are forced to start at the same time.

 

I found this but I am not sure if it applies for SCTLs inside SubVIs. Can someone verify if it applies or not to my case?

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Accepted by topic author Geont

This is an interesting question; I have thought about this myself.

 

There are some general statements that should be helpful here:

  • SubVIs on FGPA are purely cosmetic. Consider that the contents are operated in parallel to the rest of the diagram given the limitations of dataflow.
  • Any SCTLs linked to the same clock object will all operate simultaneously.

Given you are using SCTLs in the same clock domain, you shouldn't need to worry as long as you are incrementing the timestamp at the same point in each loop (ie at the end)

 

The question becomes really interesting when crossing clock domains, but all these questions are solved by using a simple target scoped FIFO and accepting a cycle of latency between the two domains.

 

If you are worried though, you could implement a loop that just counts up timestamp. Then read timestamp as a local variable in each of the subsequent loops. The local variables should all be in sync with each other even if they are not in sync with the incrementing loop.

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