LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

Simscape model Labview FPGA integration workflow example

Hi,

 

I am looking for an example workflow on how to integrate Simscape (simulink) model in to labview FPGA model. I generated HDL code out of simscape model and created an IP component in labview model. But when it was integrated with other structures, its not giving desired results as what we observed in simscape model.

 

Appreciated any help on sharing example model (simscape PMSM or inverter or combined) with completed work flow.

 

thanks

 

0 Kudos
Message 1 of 6
(1,344 Views)

Have you checked the required frequency, input & output data types? 

0 Kudos
Message 2 of 6
(1,286 Views)

Hi Gurivi,

Here is an article showing how to import an example model or algorithm written in MATLAB® or Simulink® ... into LabVIEW FPGA, and test on NI FPGA hardware connected to real-world inputs and outputs.

 

Regards)

________

Best way to thank is giving Kudos / Marking as a solution.

Message 3 of 6
(1,195 Views)

Hi there!

 

My name is Pintilie Lucian! I am an electrical engineer and I want to develop a kind of HIL simulation system!

 

I want to install the "HDL Coder Support Package for NI FPGA Hardware" in Matlab R2022b to do the same thing as this thread describes (to model power electronics circuits using SimScape on FPGA). The problem is that, every time that I input the command in Matlab:

 

hdlsetuplabviewversion("2021")

 

I get this error:

 

Error using hdlsetuplabviewversion_impl
Specified LabVIEW 2021 or LabVIEW FPGA 2021 support is not installed.
For more information refer to link.

Error in hdlsetuplabviewversion_impl

Error in hdlsetuplabviewversion (line 11)
hdlsetuplabviewversion_impl(varargin{:});

 

I have installed the following software:

- LabView Full Development 2021 SP1 f2 x32 bit (I have tried with 2020, but the same error occurs);

- LabView FPGA Module 2021 x32 bit (I have tried with 2020, but the same error occurs);

- NI R series Multifunction RIO 2022 Q4;

- IP to FPGA Conversion Utility 2023 Q1;

 

I can't do anything to get it going!

 

Any ideas are welcome!

 

Please help!

 

Thank you!

 

P.S.:  Last years I have used Digilent ZedBoard as HDL Coder Target.

To set up Vivado as a Synthesis Tool I have used the command in Matlab:

 

hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2016.2\bin\vivado.bat');

 

And everything worked like a charm!

 

The NI FPGA Synthesis tool seems to be impossible to set up, even by using the compatible and requested requirements as shown here:

 

https://github.com/ni/hdlcoder-support-package-for-nifpga-hardware

 

I have no clue how to solve it!

 

Again please help!

 

Best Regard!

0 Kudos
Message 4 of 6
(1,094 Views)
0 Kudos
Message 5 of 6
(1,029 Views)

Hi there!

 

Yes, on the MathWorks forum I have posted the solution!

 

The problem is related to the "Regional settings" in "Contro Panel". If the comma (,) is used as decimal point separator (ex. 0,5), the compiller throws this error. If the dot (.) is use as decimal point separator (ex. 0.5) everything works fine! I don't know why, because the comma is the default decimal separator world-wide... But this is not an impediment! We can change it!

 

Another problem might be considered if no "delay" blocks are introduced inside the sub-systems on signal input paths. The compiler / synthesis tool throws an error about "encrypted envelope". So, to prevent this problem you need to provide delay blocks on the input signal paths.

 

Thank you for assistance!

Best regard! 

0 Kudos
Message 6 of 6
(1,016 Views)