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Real-Time data transfer issue, from FPGA to RT

Hello  Everyone, 


I apologize if I repeat this topic, but I need help with a particular application. I have read a lot of discussions but it seems that I don't find the solution.
I have a cRIO-9068 with 5 modules of analog inputs (NI9215), and I'm using the Labview '13.
I have to read in real-time simultaneously 6 signals (3 voltages and 3 currents) and save them on the PC. The saving process works fine (I'm saving the data using TDMS functions), but I have an issue with data transfer from FPGA to RT VI. I don't know why, but no matter what I do, I don't read all the data, or I read them wrong. The FPGA reads all the 6 channels once at 50us (20kHz).
The FIFO settings are: -Requested number of elements: 1023; -Data type: FXP, Signed, 26bits/5bits.


I have attached both programs (FPGA and RT).


I will be grateful for any guidance or advice! 

I wish you the best!
Martin Adrian.

RT VI.png



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You didn't attach your code.  There are two pictures (un-editable, difficult to see, impossible to execute and study), but no VIs (file with the extension .vi).


Do you have hardware that saves data in FXP format?  My recommendation would be to keep the data in the FPGA in Integer format, gather it, put it in the FIFO, and in the RT side, use a Timed Loop to scoop it up and deal with it (including converting it to "User Units").


Bob Schor

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I don't know exactly what you mean by wrong data or not all the data but I do see one potential issue with the FIFO Read on your RT system. You're doing a 0 element read and then using the elements remaining output to do an actual read which is good but it's not guaranteed that there will be some multiple of 6 elements remaining. If you ever have say 11 elements in the FIFO and you try to read that you'll decimate the 11 element array into 6 which will cause the last 5 elements to be thrown out.


At this point, aside from losing data you'll be out of sync so the first element returned in a read will no longer be from the first channel.


I would recommend doing quotient remainder (mod) on the elements remaining output and then multiplying the quotient by 6 again to make sure you're always requesting some multiple of 6 elements.

Matt J | National Instruments | CLA
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