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Priority for conventional while loop

Hi,

 

I'm running a project in Real Time on a PXI using LabVIEW 8.5 with Real Time and FPGA modules.  The code has two parallel loops, one is a 'timed loop' running at a low frequency (200 Hz) and the second is a faster loop that is in a conventional 'while loop' structure with the timing coming off a PXI-7833R FPGA (using an interrupt line).

 

I would like to be able to set the priority of the conventional while loop to be higher than the slower timed while loop.  How can I do this?

 

If it's not possible - is there a way to switch off the timing source of a timed loop (to allow the loop to be timed off the FPGA) while retaining the ability to set its priority?

 

Thanks

 

Paul

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Paul,

you cannot set any priority level to a "traditional" while loop. There are two ways you can workaround this not using a timed loop:
- the wait-time can be referred as "priority". This works only for "traditional" while loops in comparison. Shorter waits represent a higher priority. So this is most propably not applicable for you.
- insert the while loop into a subVI. You can then alter the priority of this subVI. Disadvantage: Priority is set during implementation (or using VI Server before execution) and cannot be altered during runtime.

The best way to get this to work for you is to use a timed loop. You can enter an external clocksource for timing and still have the priority settable during runtime. Here an excerp from the LV help for timed structures:
These priorities are different from VI priorities. LabVIEW executes the timed structures at a priority level below the time-critical priority and above the high priority. The LabVIEW execution system is preemptive, so a higher priority timed structure that is ready to execute preempts all lower priority structures also ready to execute and other LabVIEW code not running at time-critical priority.

hope this helps,
Norbert
Norbert
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Why don't you just switch the conversional loop to a time loop?

So you can set the priority.

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The faster real-time loop has to be in sync with some code on the FPGA.  That's why I want to use the interrupt from the FPGA code to time this particular loop.  I'm going to try switching the clock source to external to see if that allows me to use the FPGA interrupt to time a timed loop structure (as Norbert suggested above).

If this works then it will be straightforward to set the correct priorities and my problem will be fixed.  Smiley Happy

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Norbert B wrote:
Paul,

- insert the while loop into a subVI. You can then alter the priority of this subVI. Disadvantage: Priority is set during implementation (or using VI Server before execution) and cannot be altered during runtime.


The "short" solution would be this.. 😉
 
Good description Norbert!
 
🙂

 
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