02-26-2008 04:41 AM
I'm running a project in Real Time on a PXI using LabVIEW 8.5 with Real Time and FPGA modules. The code has two parallel loops, one is a 'timed loop' running at a low frequency (200 Hz) and the second is a faster loop that is in a conventional 'while loop' structure with the timing coming off a PXI-7833R FPGA (using an interrupt line).
I would like to be able to set the priority of the conventional while loop to be higher than the slower timed while loop. How can I do this?
If it's not possible - is there a way to switch off the timing source of a timed loop (to allow the loop to be timed off the FPGA) while retaining the ability to set its priority?
02-26-2008 06:38 AM
02-26-2008 07:25 AM
Why don't you just switch the conversional loop to a time loop?
So you can set the priority.
02-26-2008 07:40 AM
The faster real-time loop has to be in sync with some code on the FPGA. That's why I want to use the interrupt from the FPGA code to time this particular loop. I'm going to try switching the clock source to external to see if that allows me to use the FPGA interrupt to time a timed loop structure (as Norbert suggested above).
If this works then it will be straightforward to set the correct priorities and my problem will be fixed.
02-26-2008 07:43 AM
Norbert B wrote:
- insert the while loop into a subVI. You can then alter the priority of this subVI. Disadvantage: Priority is set during implementation (or using VI Server before execution) and cannot be altered during runtime.