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NI FPGA - host to target DMA is transmitting all zeros

I'm having a weird bug and hoping someone can help me identify what I'm doing wrong. I've got a LabVIEW FPGA project where I'm programming a FlexRIO device and using the DMA FIFO approach to transmit data.  I used the "High Throughput Streaming" example to make this, but it's not working. 

 

In my project I have a host to target and target to host DMA fifos.  Both FIFOs are u64 FIFOs and they're configured to send 8 elements at a time. I've set them to be 16k deep, but that was an arbitrary number I picked.

 

I have two VIs: one of them is the FPGA VI shown below.  The FPGA VI receives data from the host to target FIFO and is processed with some custom VHDL I've written and instantiated using IP Integrated Block.  In my VHDL code, elements 0 and 1 are overwritten by the code, but elements 2-7 should be copied exactly to an output array "Target to Host DMA Data".  That data gets put into the Target to Host DMA FIFO and sent back up to the host.  So again, I receive 8 u64 elements from the host, I replace the first 2 elements with my own FPGA code, and return the result back to the host.

FPGA_VI.png

 

On the host side, I have a simple VI I made for testing where I can input data to the array and click a button "Load Host To Target FIFO" that transmits one DMA data packet at a time down to the FPGA.  The loop automatically reads from the Target to Host DMA FIFO by first checking to if there's any data in it.  If there's 8 elements ready to read, I read those 8 elements.  

 

Host_VI.png

 

Now here's the results.  From left to right are data arrays on each side (host and target side) of the DMA FIFOs.  As I explained, I'd expect that my FPGA code would receive a data frame, replace the first 2 elements, and forward that replaced array back up to the host.  I'm seeing this happen (highlighted in yellow) and also I have counters in the FPGA that are telling me that a valid DMA FIFO element has been sent to the target, modified, and then transmitted back to the host.  However, my issue I'm seeing is that the data I'm sending from the host to the target (the second array indicator below) is showing up with no data in it.  The FPGA is being told that there's a valid data packet in it, but the data is all zero.   

 

can anyone help me understand why I can send in an array of data on the host side and a valid data packet will show up on the target FPGA side, but the data will have been zeroed out?

 

Host-FIFO-data.png

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Just checking if someone also knows: the wire between my VHDL IP code and the Ready for Output line has a feedback node in it.  This is automatically put in, and won't let me remove it.  Does anyone know either why this happens, or whether I need to be counter-balancing that delay tap by delaying the Element and Output Valid lines going in to my VHDL IP?

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