01-17-2022 11:48 AM - edited 01-17-2022 11:52 AM
I have a CompactRIO with an 9262 module. I am trying to achieve a 1 MS/sec update rate on multiple channels of the NI 9262 per the datasheet specification.
Would someone from NI be able to provide an example of how to generate the Write I/O and Generate I/O Sample Pulse timing in FPGA user logic using the User Controlled I/O nodes? I need an example of how to interleave the writes with correct timing.
Note: Without having cycle-accurate timing via a third-party simulator (i.e. ModelSim) this is difficult for the end user.
I am curious why you advertise this way but not provide adequate documentation/example code for the end user?
01-17-2022 11:54 AM
Have you reviewed the shipping examples for this device?
01-17-2022 12:14 PM - edited 01-17-2022 12:20 PM
Yes, there is an example called NI 9262 User-Controlled Sampling (FPGA). Below is a screenshot of the example
Not very useful as there is no documentation describing how the Write I/O Node Pulse, Generate Sample Pulse, and Get I/O Write Status are generated and the related timing information.
Do you know where I can find that?
In the LabVIEW FPGA training, it said that the AO node takes ~35 ticks.
How did they achieve this number?
Also, what is the timing relationship between the AO Write Pulse and the Write Completed status pulse?
In the example code, the Write Completed Pulse controls the Generate I/O Sample Pulse how do you know what the timing looks like?
01-17-2022 02:38 PM - edited 01-17-2022 02:45 PM
Here is the output from the provided example on AO0. On AO0 6 V is showing up with periodic spikes every 1 us. From my understanding, the output should be solid 1 V or 1 V pulses from the DAC. Looks like some of the data from AO5 is coming out on AO0. This is running the stock example.
This is where a cycle-accurate simulation would be very useful. Otherwise, debugging the FPGA code is a guessing game.
Plus, here is an interesting comment on the RT Front Panel
RT Front Panel
01-17-2022 03:56 PM - edited 01-17-2022 03:56 PM
The RT is sending data every millisecond which matches up to your plot.
Do need the signal generation on RT or the FPGA?
I hear you on documentation per hardware.
Should give you a good starting point.
01-17-2022 06:26 PM - edited 01-17-2022 06:49 PM
So I'm "simulating" some code using Simulated I/O, trying to get the analog out buffer to preload as described in slide #8 of the powerpoint that I randomly stumbled across on the forum.
For some reason during my "simulation", the Write Complete signal never goes high. How do you make Write Complete go high?
There is definitely data getting written to the analog output node in the simulation. I can see the loop run and the data go into it. The data changes back and forth between -10 and 10. There should be a pulse on the Write node. Why does Write Complete never go high?
I assume "Write Complete" is some kind of acknowledge that comes from the C series bus (SPI) that NI didn't document anywhere or have any information on. Is this correct?
This is just me guessing because nothing is written anywhere.
The reason I assume I need to wait for Write Complete to toggle twice is because that piece of code appears to be in the User Controlled I/O example for the 9262. The example code checks to see if Write Complete asserts twice. When Write Complete has asserted twice, Generate Sample Pulse goes high, the loop stops, and Sample Pulses are generated every 1 us. Is this correct?
So, how would I get this to work in "simulation"?
How about since I paid a bunch of money for a cRIO and several modules I get a real simulation environment like every normal person developing FPGA's.