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More detailed compilation timing report?

How does one obtain a more detailed timing report after compilation (even if compilation succeeds)? "Met MHz maximum" is often not enough to gain better understanding about how my designs are impacted by logic changes. The Xilinx log file asks the user to "run report_timing_summary" to obtain a more detailed report however it isn't clear to me how to do this. Chasing this a little deeper, I understand that Xilinx uses the Tcl scripting language from Vivado to execute commands like "report_timing_summary" but I've never tried to open the underlying Xilinx files that are generated by LabVIEW-initiated compilation. Which exact files are involved, where are they located, and how do I use Vivado/Tcl to analyze them?  


(This PDF will be helpful once I have the files)


Thank you in advance.

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I've look up some possible recommendations, maybe this link could help you. Other link that could help is this (propably you already saw it), that have a relationship with this one, referring to Compilation Status Window Reports Available from the Compilation Status Window (FPGA Module), respectively.


By the way, Compatibility between Xilinx Compilation Tools and NI FPGA Hardware, this link could help you to use Xilinx Tools on your project.

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Another option - 


FPGA Target -> Build Specs -> Create -> Vivado Export.


When the export process is complete, select "Open project in vivado" on the resulting popup.  You can do this later by right clicking the vivado build specification.  From here, you can view all the constraints in a monolithic .xdc including any FAMs you've used and imported.


You can use all the usual Xilinx tools from there.  Specifically, on the lefthand navigation tab, choose "Implementation" and run implementation.  Then you can use the timing command you described in the TCL input window, or using the GUI. You can build the .lvbitx as well - when the Vivado export is made, there is a specific LVFPGA-generated script that is run on the resulting .bit file, that wraps the .bit into the xml wrapper matching your top level VI's IO from the labview perspective.  

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