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Implement Savitsky-Golay Filter on LabVIEW FPGA

Has anyone implemented Savitzy-Golay filter in LabVIEW FPGA? Please let me know the implementation.

 

-Thanks

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See https://forums.ni.com/t5/LabVIEW/How-to-implement-Savitsky-Golay-Filter-on-FPGA/td-p/3339998


Its math may be similar (convolution) to other math functions that exist.


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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Assuming you know your coefficients already or can use host functions to calculate your coefficients and download them to the FPGA then it should be a simple correlation function effort.  It might be easiest to implement using an FIR filter core from Xilinx if you know your coefficients ahead of time.

Systems Engineering - National Instruments
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Hi,

Could you please elaborate the simple correlation function part in FPGA. I know the coefficients calculation, which will give me a matrix of coefficients. How to multiply the matrix with the input signal in a single-cycle timed loop. For example, I am attaching a screenshot of filter design. How to perform the coefficient multiplication (red highlighted box) in fpga. My input signal is a continuous digitized voltage signal.

 

Thanks,

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I maybe wrong here but if you are dealing with a continuous signal you shouldn't have to deal with the first k rows or the last k rows because those only serve to handle cases where you are missing side points.  In an continuous signal you will always have enough side points.  Of course except for the first "side points" number of samples but you can disregard that because it is just a short transient condition that is not worth complicating the code to handle.

 

The NI example uses 12 side points as default so my explanation will use that as well.  Optimal implementation would depend on a lot of factors including the ratio between processing clock and sample clock.  If your FPGA is fairly empty and this is most of what will be added to the FPGA then I would keep the design simple.  Only complicate things if necessary when resources get tight.  The operation you are looking to implement is a MACC (multiply and accumulate).  You will need to have storage for 2*k + 1 (25) values.  The easiest way to handle this is to serialize a bunch of feedback nodes.  Using a memory like a BRAM would be more compact but then you don't have access to every value on every clock.  You can use the high throughput multiply 2*k+1 times where each gets one value from one of those feedback nodes and one from a coefficient loaded from the host or hard-coded.  Then use the high throughput add blocks to create an adder tree to sum all the values.  Note that there will be latency between input and output.

 

If you've used the Xilinx IP in LabVIEW FPGA you could also implement this with an FIR filter because it also performs the same operation.  Or you could implement it directly using the DSP48E(1).  Since I don't know your LVFPGA experience level I don't want to go too far into that.

 

Good luck,

Andy

Systems Engineering - National Instruments
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Thank you Andy for the detailed explanation. Now I understand what did you mean by getting the coefficients and simple multiply and accumulate as FIR filter. I have experience in implementing the FIR filter, so now I am able to implement the SG filter with the coefficients precalculated.

Thanks!

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