How to get TSN synchronized cRIO clock time onto the FPGA for timestamping high-speed data?

[CaseyN21]

Hello,

I have a cRIO 9049 which is synchronizing its clock to a TSN grandmaster clock on the network. I would like to do high-speed data acquisition with the FPGA and have the data timestamped with a TSN quality clock at the time of acquisition (must be done on the FPGA). The easy solution would be to just get the timestamp when the data arrives to the RT side through a FIFO. However, I don't like the added latency of going through the FIFO and would like 100 ns quality time on the FPGA.

Is there a way to connect the RT clock/System Clock/TSN clock to the FPGA so I can timestamp my data on the FPGA.

Example:

I am collecting 50 kHz analog input data from a 9239 card in a cRIO slot. The FPGA loop is running at 50 kHz getting fresh values from the 9239 card and loading the data into a FIFO which later gets turned into a waveform on the RT side. I would like to read the "RT clock/System Clock/TSN clock" time in that 50 kHz loop to ensure my timestamp is within 100 ns of the grandmaster time so my t0 value in the waveform is very accurate.

Any ideas on how to implement this? In the past we used the timekeeper and NI 9467 but we have ditched that component in hopes that TSN time will meet our synchronization needs.

Thanks!

[CaseyN21]

Took a stab at using the FPGA timekeeper with updates from the System clock sent to the FPGA through an indicator write and timed with an interrupt.

FPGA Code:

RT Code:

This code seems to be able to keep the FPGA time sync'd with the System clock within 15 us which is pretty good.

Anyone have ideas to lower this offset? Also, I understand that it will never be perfect but looking for suggestions to improve the code.

Thanks,

-Casey

[Jacobson]

You should be able to directly access the TSN synchronized time from the FPGA on a 9049.

When you add a new FPGA target to a 9049 you should get a folder of FPGA I/O items called "Time Synchronization". I think the "Time" item will give you what you're looking for.

[CaseyN21]

Thanks for your reply! That makes sense that it would be the system time on that FPGA IO. Do you know where that is noted in the documentation? The cRIO user manual and LabVIEW help manual does not cover this, unfortunately.

-Casey