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Host VI and HDL Cosimulation Timeout Problem

LabVIEW 2017 or some earlier versions support host VI and HDL cosimulation by Questa Sim simulator. However, there is a timeout that after run a "Open FPGA VI Reference Function" node in a host VI to open the simulator, the simulator has to finish loading the HDL design within 60 seconds. Otherwise, the "Open FPGA VI Reference Function" node throws a timeout error. Unfortunately, there is no way to modify this timeout value. This fixed timeout limits the simulated HDL design sizes. Does anyone have a solution such that we can do cosimulation with any HDL design size?

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