I am relatively proficient with LabVIEW FPGA but any built-in function called convolution interleaver is unknown to me. I am however not even familiar with the concept.
I Googled it and found this page: https://surf-vhdl.com/how-to-implement-a-convolutional-interleaver/
Is this what you are asking for? If I understand correctly a convolution interleaver rearranges the bit order before streaming the data on some communication link in order to make the communication link less receptible to errors. Implementing such a technique in LabVIEW FPGA is quite doable, one could even just follow the VHDL code provided in the link.
But I am afraid I don’t have any solution to share.
in normal labview we may decimate into subpart and access them and we can add some interleaving bits
but since in fpga i can access only in one by one element right?
so how the conceot changes
I am afraid I don't fully understand you.
Are you asking about specific implementation techniques? It's hard for me to answer since I don't fully understand your specific problem nor your algorithm. And as I said I have never implemented any convolution interleaver in LabVIEW myself.
But if the link I provided matches what you want to do I would probably follow what is depicted in Figure 2. I would take the data from host using a host-to-target FIFO, reading each byte from that FIFO and then send each bit through a case structure with four diffrent cases where each case would correspond to a different delay. Or something like that.