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Electrical power calculation in FPGA VI with digital filters

I've skimmed through a few relevent articles and discussions on this topic but it seems some of the difficulties in the past might not be the case any more in newer versions of LabVIEW FPGA. I'd like to get some overall up-to-date assessment and tips before I invest serious time in this. I have PXI-8106/8108 (controller) and PXI-7813R (FPGA RIO). The version of LabVIEW is 2011 SP1. Currently, FPGA VI simply takes input data and sends them to the DMA FIFO. The diagram below shows an electrical power calculation subVI. Basically, I'd like to know if it would be possible to move this subVI into the FPGA VI with full functionality. In this program, 6 different sampling frequencies (1600, 1920, ..., 10240 samples/s) can be chosen by the user. As shown in the diagram, the subVI uses DC reject, low-pass, phase shift and notch filters. Each of them will need 6 sets of coefficients for different sampling frequencies. Are there some important restrictions imposed by FPGA module that you have to be aware of when you design digital filters? Any relevant information and tips will be appreciated.

 

W1__calc1d.png

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Let me explain my situation better with more diagrams. The following diagram shows how the DCR filter is set up with different coefficents for different sampling rates. I'd like to put several filter modules of this kind in the FPGA VI with some arithmetics as shown in the previous diagram.

 

DCR.png

 

The below is the FPGA VI taking data from 16 input channels (NI 9229).

 

FPGAd.png

 

The goal is to send both basic power calculation results and raw input data (because there are more complex calculations to be done in the host VI) to the DMA FIFO in expectation of significantly reduced load on the controller. How viable is this plan? Will it certanily improve the system performance? Will there be enough resources in the FPGA? I'd like to get some big pictures first.

 

I began looking into this:

Designing a Fixed-Point Filter (Digital Filter Design Toolkit)

 

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Hey MemoryGrowth,

 

I don't see anything that would suggest that this VI would not work on the FPGA. However, I don't know what is inside of many of the subVIs that you have so I can't tell you for sure that there isn't something in them that might not work on the FPGA. It is common practice to offload most of your signal processing to the RT VI and leave your FPGA open for I/O. However, if the VI fits on your FPGA there isn't really any reason not to do it. The only real way to find out if your VI will compile on the FPGA is to try it. If anything breaks in the VI when you move it to the FPGA target in your project, or anything happens during the compile then we could troubleshoot from there. 

 

Good Luck,

 

Doug B

Applications Engineer
National Instruments
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Thanks for the comment. Those sub VIs are all digital filters.The DCR filter's block diagram is shown above as an example. The reason why I'd like to implement the calculation module inside the FPGA is because the current calculation load on CPU from the host RT VI is very heavy. Sometimes the system will crash. I will try to write and compile a simpler version of the code for the FPGA.

 

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