I'm trying to write an FPGA vi to use 2 channels on the 9870 RS232 cRIO module with the 9074 integrated chassis/controller. Basically, I use 2 DMA FIFOs to transfer data between RT and FPGA, however I always get the error that the specified target only supports 3 DMA FIFOs and to remove one or more. The problem is, I only use 2 FIFOs! I deleted the host-to-target FIFO and it is compiling now, but I would prefer to use the FIFO.
I have read that some cRIO controllers do not support host-to-target FIFOs, but I cannot find documentation on this anywhere. Is this the case for the 9074, or is there something I am overlooking?
Yes I am running in hybrid mode, although I was unaware of the DMA channels that the Scan Engine uses. Is there documentation on this anywhere? Since I have a very high density cRIO system (32AI, 16AO, 32DIO, 32DO, 16TC, possibly also another 32AI and 16TC in the near future) and low sampling rate requirements I wanted to avoid the FPGA as much as possible, but am forced to use it for the RS232 module.
So if I only have 1 DMA channel available to work with, what would you suggest as far as host-target communication for my RS232 module? The developer's guide strongly advises not to use array front panel controls for performance reasons, but most of my serial communication is <30B at a time and the fastest speed is 28.8k baud. Would using arrays in this case have that much of a performance impact?
Finally, another question, the 9074 has a 2M FPGA, does anyone know approximatly how may slices the scan engine uses? Because right now I have a simple FPGA vi and it uses 47% of my slices, so I was hoping that most of that was overhead from the scan engine...
Have a look at the following documentation:
Using arrays might effect the performance by a lot. I would definitely recommend not using it but you can try and see what goes on. With regards to incorporating RS 232 communication, you might be better off calling NI support and asking them for help on this; I have not worked with RS232 along with cRIO, so can't help you much on this. Be sure to post back if you are able to resolve the issue in any way.
I am sure 47% of the slices in the Scan Engine since when you run the Scan Engine, it does use a compiled FPGA bitfile to communicate with the C Series modules.
Number of DMA channels (Target to host) ?
I tried to read 2 FIFO's from the FPGA (with 2 separate triggers) but somehow it doesn't work. I attached some screenshots so one has an idea what I programmed and what happened after I compiled the FPGA code (because I don't have all the hardware yet, there are a lot of Booleans and constants on the FPGA diagram> later to be replaced by physical channels). It seems there is only one DMA channel for transferring data from FPGA to Host (I use the CRIO 9074).
Does somebody know what is going on and how I probably can solve this matter ?
Freek van Uittert
University of Technology Eindhoven
You've defined some "Real Time Scan Resources". I assume that puts the FPGA in hybrid mode.
You're right. There where some modules (not in the cRIO) from a recent project hided in a former directory. After deleting them out of the project I got 2 additional DMA resources.
Thanks for your help.