DDS Compiler (Xilinx Coregen IP) maximum achievable clock rate

[SunJab]

Hi,

I am using labview FPGA2011 and FlexRIO 7965R (i.e. Virtex5 SX95T). I have compiled a sinusoid generater using the built in Xilinx Coregen IP named 'DDS Compiler'. The output of DDS Compiler is sent to the host VI using DMA FIFO. My SCTL runs at 346MHz, as the largest clock that can be provided is 346.666MHz. The code according to DDS Compiler data sheet (DS558) with the configuration settings that i have used, should burn at 450MHz (mentioned in cloumn 4  of Table8 on page 28). But my code gives a maximum achievable clock rate of 350.63MHz. I have attached my code and images of the compilation results. Can somebody check and tell me why am i not getting the 450MHz rate? Is there any limitation on the clock rate due to the VI scoped or DMA FIFOs?

Thanks

[Dave.T]

Hi Sandee, 

What are you planning on doing with this sine wave?  Are you using a FlexRIO Adapater Module(FAM)?  

The reason you can't get anything higher than 346.66MHz is because the clock that is being generated from is a 40 MHz clock.  Once you multiply it up that high, the accuracy of the frequency is not reliable.  

The beauty of the FlexRIO is that you are able to bring in external clocks with several of our FAMs.  These external clocks are piped directly to the FPGA.  On top of that, if you're using the 6587 FAM, for example, you're able to generate up to a 500 MHz clock on the FAM, and provide that to the FPGA.  

To do that, you first add your adapter module to the project

Right click on your fpga target -> select new FPGA Base clock - > IO Module clock 0 from the drop down.  

Then specify your frequency to be 450 or 500, whatever you want it to be. 

Then on your block diagram, you'll provide your single cycle timed loop with the IO Module Clock 0 as the source. 

I'm going to compile it now and I'll update with the results. 

[Dave.T]

It compiled without issue.  

If you're getting any weird data or missing data in your FIFO, try implementing the target scoped FIFO in Flip Flops instead of block ram.  Since the block ram is physically in a different location than the slice fabric, the propagation delay might be too great to make it there in 450 MHz.  Implementing it in the flip flops means the signal needs to propagate a shorter distance and has a greater probability to ready by the next clock tick. 

[SunJab]

I'm not using FAM right now but i'll be using it in the future. Actually, I have to implement DDC in FPGA. For this i need to multiply the incoming signal with sine and cosine waves. I was just wondering why am i not able to get the same results as mentioned in DDS Compiler data sheet.

As you have mentioned that using 6587FAM i can generate clock up to 500MHz and provide that to FPGA. So, for example if i set the clock rate of SCTL to 450MHz, the code inside should all execute in a single cycle. But the problem is I can't achieve above 350.63MHz for DDS Complier, whereas the data sheet says it should burn at 450MHz. So, if I understand correctly, its probably because writing to the target scoped FIFO is taking long. Flip-flops provide the fastest performance but for large FIFOs can i implement using flip-flops?

Thanks

[SunJab]

The help also says you can not use FIFOs implemented through flip-flops and LUTs across multiple clock domains.

[Dave.T]

Hi Sandee, I'm looking more in to this for you.  

Thanks for being patient. 

[Dave.T]

Hi Sandee, 

Unfortunately when we're talking about a single cycle timed loop, there are other things besides the DDS that are going to limit the max speed to around 250 MHz.  

For this applications, I'd recommend running two DDS cores in parallel, then searlizing their output into the adapter modules socketed clip node, or wherever the data is eventuallg going.  

There may be a better architecture that will meet your needs.  Can you give me a bigger picture of what you're trying to accomplish?