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Compiling Target FPGA application, and invoking in host VI

I can execute a target application on FPGA with no problems, everything runs fine...however.

When I invoke an FPGA VI from a host after compilation the target application is running extremely slow. WHat are the appropriate steps after compiling a FPGA VI to invoke that application from a Host VI?

Something isn't adding up!
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So, you're using the Open FPGA VI Reference function and controlling the
FPGA VI with a Read/Write Control node? You should be able to read and
write controls and indicators in groups of about 10 with a 1 ms wait between
operations and still have excellent control and monitoring of the FPGA, with
minor loading on the host computer. Could you describe your vi's and which
part is running slow?

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