Hi ,
Im using the FlexRio Kintex 7 Board for my Design. Im using 6585B adapter.
I needed 4 different clocks , 3 of the clocks i generated by PLL which was generated by Vivado (20Mhz , 100Mhz , 100Mhz Phase shift 180) . the forth clock is a very slow one , its 40Hz, so i wrote a VHDL code for it (a Counter) .
I planned to use the internal clock of 40Mhz , to be the clock for the PLL and for the Counter(40Hz).
I have few questions :
1. How can i route the the internal clock of 40Mhz to be the input for the PLL and the counter ?
2. For timing performance , Should i make CLIP and put it to labview or Leave it as a VHDL Code and insert it to adapter VHD File ?
3. Is there a way to synchronize between all of them ?
