Hello LabVIEW FPGA folk,
I have a project on FPGA target X, and I ran out of resources.
I want to recompile it on Target Y to check if I'll be better off.
I've seen this article
Which explains the steps needed to port from target to target.
But in my case I have Multiple FIFO's and registers declared ... I really would not want to go though the process of re-declaring them again, not manually this could be error prone.
Please see screenshot for clarification on what I mean.
So are there any tips any of you FPGA gurus can give me to help me out?
Is there a way I could copy out a section of the LV Proj XML or somethig so that I don't have to re-declare everything by hand like a robot?