This may be a fundamental question, but can you or should you, read the same analogue input node from a CRIO module in multiple places in FPGA LV?
I.e in two separate sub VIs read the same AI?
you can read in multiple places.
The "should" boils down to "does it hurt your performance"? It has side effects to access the same module/port/channel in multiple places: you may not get the sample rate (or loop iteration time) you expect...
Reading a single point AI on an FPGA is pretty fast. But it is much slower than reading from a variable. So if you can read in a single loop with some kind of indicator that a new read has taken place (FIFO, or setting a boolean flag) then it probably would be a better design from a performance stand point. But it does add complexity and if performance isn't an issue maybe the benefit isn't really worth it.
Just to add to the answers...
AFAIK, Multiple nodes will read multiple times. So it's not the last value that is returned, each node acquire a new value. As mentioned, this could change the expected data rate, but it also means the values you read (potentially simultaneously) do not give the same value.
This may be a fundamental question,
Nothing wrong with that!