CRIO FPGA doesn't load on cold boot

[mmalluck]

I'm looking for a list of gotcha's that may explain why I'm having issues.

Essentially on a cold reboot (power cycle) of the cRIO, it appears that the FPGA section of my code is not executing. If I reboot the cRIO via MAX the code functions as expected. If I execute the code via the project explorer it operates as expected.

I'm developing on labview 8.6 with a cRIO-9014 host and a cRIO-9104 chassis. The host is executing a RT application on startup. This application loads the FPGA, makes a couple of calls to the FPGA.VI to initialize the unit (utilizing a couple of interrupt calls) and enters the main loop. The main loop gathers information from the FPGA via the DMA and then processes the info.

I know the host VI is executing as I can monitor it via the web interface on the controller, but it does not appear the FPGA is interacting with it.

I've tried adjusting the RIO device setup to autoload the FPGA VI during device power-up and device reboot. I've also set the FPGA VI to run when loaded. All setting result in the condition shown above. Is there a setting somewhere that I'm overlooking or do I need to try something else?

[Jeremy_B]

Hi mmalluck,

It sounds like you need to download the FPGA bitfile to flash.  You can do that in the RIO Device Setup.  There will be a tab which lets you select a bitfile and download it to the flash memory (the next tab over will have the settings for autoloading the bitfile, which you appear to have set correctly).

[mmalluck]

Thanks Jeremy,

After striping down my code to post , I stumbled upon the root of my problem. It appears some of the 3rd party hardware I'm using has different boot-up times depending if a cold boot has just occured or if the unit is warm booted. On cold boot I was trying to begin executing before the hardware was ready. A slightly longer boot-up wait and everything is working as it should.

Thanks again for your time.