Best way to share data on RT Linux

[DR2027]

Hello,

Trying to share data on NI PXI RT Linux without causing undue CPU usage or Blocking is a major concern for many of us. Here is the general system design:

Multiple loops that read or write data at 10 to 1000 Hz (10 to 5000+ Hz would be better)

• 50 to 100 VIs running in parallel performing various tasks
• Tasks can be read/writing I/O, PIDs, calculations, alarms, communications with external devices etc.
• Each task writes an array of values (array size varies 10 to 500 elements) to a module global variable (might change to shared variable with RT single element FIFO to reduce blocking on writes)
• Any one of the 50 to 100 VIs might need to read any other VIs data so there could be blocking happening from multiple reads of the module global variable (or FIFO)

Considering the speed at which I want some of the loops to iterate what might be the best architecture for this monster?

[ZYOng]

Looks like VeriStand is exactly what you need. The VeriStand Engine uses the non-blocking RT-FIFO.

[Bob_Schor]

When you say "share data on NI PXI RT Linux without causing undue CPU usage", do you mean within the RT Target (such as a CompactRIO) or between the Host (PC) and the RT Target?

For the former ("within"), I've used Asynchronous Channel Wires (you need at least LabVIEW 2019 to do this "properly" on an RT Target), and RT FIFOs if going between the Target and its FPGA.  For the latter ("between"), I've used Network Streams. 

I've achieved (burst) speeds of 16 channels of A/D from 16 custom-made, SPI-managed circuit boards with sampling at (I believe -- haven't looked at it recently) at least 10 kHz.  These data go from the FPGA to a Timed Loop on the RT Target, and the burst of data are transmitted to the Host (and streamed to the PC's disk) via Network Streams.  Transmission within Host and Target are both accomplished with Channel Wires.

Bob Schor

[raphschru]

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@Bob_Schor wrote:

[...] and RT FIFOs if going between the Target and its FPGA.  For the latter ("between"), I've used Network Streams. 

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I guess you meant DMA FIFOs for communication between RT (which you call "Target") and FPGA.

RT FIFOs are for communication within an RT application.

[Bob_Schor]

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@raphschru wrote:

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@Bob_Schor wrote:

[...] and RT FIFOs if going between the Target and its FPGA.  For the latter ("between"), I've used Network Streams. 

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I guess you meant DMA FIFOs for communication between RT (which you call "Target") and FPGA.

RT FIFOs are for communication within an RT application.

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Right you are.  I think of LabVIEW Real-Time as Host (PC), Target (something running a Real-Time OS and communicating with the Host), and (optionally) FPGA, which communicates with the (RT) Target (via a DMA FIFO, thanks for the correction).

[DR2027]

Thanks for the reply Bob,

• My application is running on a NI PXI platform in NI Realtime. I am not using an FPGA (unless I need to)
• Each VI is running asynchronously producing an array of data and will write to a single element FIFO to prevent write blocking with reads.
• Each VI needs data as input because it's calculation is partially based on another VI's output data

Here's the problem:

• Since each VI must read from another VI's single element FIFO there could be read blocking because many VI's may need to read the same FIFO at the same time to get the data need. How do I prevent this blocking on reads?