Arbitration of read/write of FPGA Memory Array

[eruffaldi]

I would like to access in read/write to a FPGA Memory Array from multiple location at different clock domains, with FPGA Memory backed by Lookup Table.

Is the arbitration performed per-address of for the whole array?

In the documentation https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgaconcepts/fpga_memory_items/ it mentions issues only for simultaneous access for FPGA Memory backed by Block Memory.

Thanks,

Emanuele

[Intaris]

No, it's not performed per address.

It's per callsite. Per access.

Timing will vary depending on whether another process is currently reading / writing or not.

[eruffaldi]

Then if I have 100 separate callsite, even in different VIs, writing the same Memory Item at different addresses (0..100) they will arbitrate the access to the same Memory Item resource.

[Intaris]

That's my understanding, yes.