RFFE IP »
This IP implements MIPI RF front end (RFFE) communication, including support for both master and slave functionality.
Description: The MIPI RF Front End (RFFE) specification was developed to form a standard bus protocol for devices in a radio frequency signal path to minimize noise coupled into the devices from digital signals and to solve high configuration speed requirements for MIMO applications. RFFE busses allow only a single master that drives a clock (SCLK) and data (SDATA) to multiple slave devices; the very low pin count (two pins) benefits overall system simplicity. This IP includes an RFFE Master suitable for controlling an RFFE bus and an RFFE Slave. Note that the RFFE standard uses signaling levels (1.2 Volt or 1.8 Volt) that are not directly compatible with NI devices which use 3.3 V TTL digital I/O. External signal conditioning circuitry may be required for any RFFE bus that is interfaced to NI hardware.
Xilinx Virtex-6 LX195T
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