RFFE IP

[Ryan_V[DE]]

RFFE IP » This IP implements MIPI RF front end (RFFE) communication, including support for both master and slave functionality.

Description:  The MIPI RF Front End (RFFE) specification was developed to form a standard bus protocol for devices in a radio frequency signal path to minimize noise coupled into the devices from digital signals and to solve high configuration speed requirements for MIMO applications. RFFE busses allow only a single master that drives a clock (SCLK) and data (SDATA) to multiple slave devices; the very low pin count (two pins) benefits overall system simplicity. This IP includes an RFFE Master suitable for controlling an RFFE bus and an RFFE Slave. Note that the RFFE standard uses signaling levels (1.2 Volt or 1.8 Volt) that are not directly compatible with NI devices which use 3.3 V TTL digital I/O. External signal conditioning circuitry may be required for any RFFE bus that is interfaced to NI hardware.

Additional Documentation:

• After Installation - C:\Program Files (x86)\National Instruments\LabVIEW 2012\user.lib\_NI RFFE IP\documentation\NI 5644R MIPI RF Front End (RFFE) Example.pdf

Compatibility:

• LabVIEW Versions: 2012
• Verified hardware targets: NI PXIe-5644R, NI PXIe-5645R
• Links to relevant examples: RFFE Example for the NI PXIe-5644R

Dependencies:

• none

Performance:

• 2 wire interface
• programmable clock frequency

FPGA Footprint:

Xilinx Virtex-6 LX195T

• 0.9% / 1069 LUTs
• 0.6% / 1407 Flip-Flops
• 4.7% / 16 Block RAMs
• 0.0% / 0 DSP Slices
• 125 MHz clock rate

Latest Version:

• RFFE IP 1.0.0 (LabVIEW 2012)

Previous Versions:

• none available

Note: All source on this community is distributed using VI Package Manager (VIPM). For more details on VIPM, please read A Note on VI Package Manager