From Friday, April 19th (11:00 PM CDT) through Saturday, April 20th (2:00 PM CDT), 2024, will undergo system upgrades that may result in temporary service interruption.

We appreciate your patience as we improve our online experience.

Examples and IP for Software-Designed Instruments and NI FlexRIO

Showing results for 
Search instead for 
Did you mean: 

Power Servoing IP

pa servo.png

Power Servoing IP »


This IP uses an FPGA-based control loop to rapidly adjust device output power to reach a desired input power, when an load or amplifier of unknown gain is connected between the output and input.


Description: This IP is designed to level the output of an RF power amplifier by iteratively measuring its output power and adjusting the supplied stimulus. These measurements and adjustments are performed continuously, as opposed to traditional techniques which make these measurements and adjustments in series, with significant latency between each. The parallel leveling in this IP is able to achieve much faster performance than traditional methods, placing the power amplifier into a known state so that subsequent measurements can be performed, decreasing overall test time.


Additional Documentation:


  • After installation - C:\Program Files (x86)\National Instruments\LabVIEW 2012\user.lib\_NI Power Servoing IP\documentation\Hardware Power Leveling for PA Test.pdf







  • none




  • 1 input I/Q pair per loop iteration / clock cycle
  • 18-bit fixed point
  • 1 channel


FPGA Footprint:


Xilinx Virtex-6 LX195T


  • 1.9% / 2333 LUTs
  • 1.1% / 2739 Flip-Flops
  • 2.6% / 9 Block RAMs
  • 0.6% / 4 DSP Slices
  • 160 MHz maximum achievable clock rate (empty FPGA)


Latest Version:



Previous Versions:


  • none available


Note: All source on this community is distributed using VI Package Manager (VIPM). For more details on VIPM, please read A Note on VI Package Manager

Ryan Verret
Product Marketing Engineer
Signal Generators
National Instruments