Examples and IP for Software-Designed Instruments and NI FlexRIO

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Power Servoing Example for the NI PXIe-5644R

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Power Servoing Example for the NI PXIe-5644R »

This example uses an FPGA-based control loop to rapidly adjust VST output power to reach a desired input power, when an load or amplifier of unknown gain is connected between the output and input.

Description: This example is designed to level the output of an RF power amplifier by iteratively measuring its output power and adjusting the supplied stimulus. These measurements and adjustments are performed continuously, as opposed to traditional techniques which make these measurements and adjustments in series, with significant latency between each. The parallel leveling in this IP is able to achieve much faster performance than traditional methods, placing the power amplifier into a known state so that subsequent measurements can be performed, decreasing overall test time.

Additional Documentation:



FPGA Footprint:

Xilinx Virtex-6 LX195T

  • 38.6% / 48230 LUTs
  • 23.2% / 57845 Flip-Flops
  • 39.5% / 136 Block RAMs
  • 33.0% / 211 DSP Slices
  • >90% compile success rate

Latest Version:

Previous Versions:

  • none available

Note: All source on this community is distributed using VI Package Manager (VIPM). For more details on VIPM, please read A Note on VI Package Manager

Ryan Verret
Product Marketing Engineer
Signal Generators
National Instruments