Examples and IP for Software-Designed Instruments and NI FlexRIO

cancel
Showing results for 
Search instead for 
Did you mean: 

NI PXIe-5645R 6 GHz Vector Signal Transceiver, with Baseband I/O

5645r 104x82.png

NI-RFSA and NI-RFSG Instrument Driver FPGA Extensions Examples

<hr>

Instruction Sequencer.png

NI Instruction Sequencer and SPI Example for the NI PXIe-5644/45R »

This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with the instruction sequencer and SPI IP to create FPGA personalities for the NI PXIe-5644R and NI PXIe-5645R that have the ability to issue sequences of SPI commands for hardware-timed DUT control.

i2c.png

NI I2C Host Example for the PXIe-5644/45R »

This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with the NI I2C IP to create FPGA personalities for the NI PXIe-5644R and NI PXIe-5645R that have the ability to implement I2C communication for hardware-timed DUT control.


rffe.png

NI RFFE Host Example for the PXIe-5644/45R »

This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with the instruction sequencer and SPI IP to create FPGA personalities for the NI PXIe-5644R and NI PXIe-5645R that have the ability to implement RFFE commands for standard specific hardware-timed DUT control.

spi.png

NI SPI Host Example for the PXIe-5644/45R »

This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with the instruction sequencer and SPI IP to create FPGA personalities for the NI PXIe-5644R and NI PXIe-5645R that have the ability to issue sequences of SPI commands for hardware-timed DUT control.

Static Digital.png

NI Static Digital Host Example for the NI PXIe-5644R/45R »

This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with the instruction sequencer and SPI IP to create FPGA personalities for the NI PXIe-5644R and NI PXIe-5645R that have the ability to implement static digital communication and control.

pa servo.png

Power Servoing Host Example for the NI PXIe-5644R/45R »

This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, to level the output of an RF power amplifier by iteratively measuring its output power and adjusting the supplied stimulus.

Gaussian Noise.png

NI Noise Generation Host Example for the PXIe-5644/45R »

This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions to adds AWGN to a waveform in real time on the FPGA of a PXIe-5644/45R. The noise is generated using the NI Noise Generation IP.

Slot Power IP and Example.png

Slot Power Host Example for the NI PXIe-5644R/45R»

This example implements Slot Power measurments via RFSA and the NI Slot Power IP Host API.

JTAG.png

NI JTAG Host Example for the PXIe-5644/45R »

This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with JTAG standard signal commands for use in boundary scan testing of ICs and printed circuit boards.

FIFO streaming.png

Streaming Host Example for the NI PXIe-5644R »

This example uses NI-RFSA and NI-RFSG instrument driver FPGA extensions, along with the Stream Controller IP to stream data from the host VI to the output port of the NI PXIe-5644R as well as from the input port of the NI PXIe-5644R to the host VI. This example also provides a template for setting up peer-to-peer streaming with another device.

Verified Application IP

<hr>

DSP

channel emu.png

Channel Emulation IP »

This IP implements inline, real-time DSP in LabVIEW FPGA to apply arbitrary channel models to RF data. Fading profiles are computed in real-time on the host, and dowloaded to the FPGA where they are interpolated and applied to the data stream.

Instruction Sequencer.png

NI Instruction Sequencer IP »

This IP contains a memory to hold sets of instructions, called sequences, which can be issued from the IP on the FPGA to another component on the FPGA, such as a digital protocol generator. This facilitates FPGA-based reconfiguration.

Gaussian Noise.png

NI Noise Generation IP »

This IP enables the generation of both uniform and additive white Gaussian (AWGN) noise using an NI LabVIEW FPGA device.

Slot Power.png

Bandwidth Power IP »

This IP uses an FPGA-based algorithm to calculate power in an input signal across the entire bandwidth.

Programmable Filter.png

Programmable Filter IP »

This IP implements a 33 programmable tap FIR Filter on an FPGA.

Slot Power IP and Example.png

Slot Power IP »

This IP uses an FPGA-based algorithm to calculate power in an input signal across discrete time slots.

FIFO streaming.png

Stream Controller IP »

This IP controls the writing and reading of data to and from FIFOs on the FPGA.

Control

pa servo.png

Power Servoing IP »

This IP uses an FPGA-based control loop to rapidly adjust device output power to reach a desired input power, when an load or amplifier of unknown gain is connected between the output and input.

Digital Protocols

i2c.png

I2C IP »

This IP implements inter-integrated circuit (I2C) communication, including support for both master and slave functionality.

spi.png

SPI IP »

This IP implements serial peripheral interface (SPI) communication, including support for both master and slave functionality.

rffe.png

RFFE IP »

This IP implements MIPI RF front end (RFFE) communication, including support for both master and slave functionality.

Contributors