I2C IP

[Ryan_V[DE]]

I2C IP » This IP implements inter-integrated circuit (I2C) communication, including support for both master and slave functionality.

Description: Inter-Integrated Circuit (I2C) buses are commonly used to communicate between a controller (master) device and a target (slave) device. I2C buses require two lines for communication: clock (SCL) and serial data (SDA). This IP contains LabVIEW FPGA code for both an I2C master and an I2C slave.

Additional Documentation:

• After Installation - C:\Program Files (x86)\National Instruments\LabVIEW 2012\user.lib\_NI I2C IP\documentation\NI 5644R Inter-Integrated Circuit (I2C) Example.pdf

Compatibility:

• LabVIEW Versions: 2012
• Verified hardware targets: NI PXIe-5644R, NI PXIe-5645R
• Links to relevant examples: I2C Example for the NI PXIe-5644R

Dependencies:

• none

Performance:

• 7 and 10 bit addressing
• Up to 8 data bytes
• Read and write access
• Programmable clock frequency

FPGA Footprint:

Xilinx Virtex-6 LX195T

• 0.7% / 839 LUTs
• 0.4% / 907 Flip-Flops
• 0.0% / 0 Block RAMs
• 0.0% / 0 DSP Slices
• 40 MHz clock rate

Latest Version:

• I2C  IP 1.0.0 (LabVIEW 2012)

Previous Versions:

• none available

Note: All source on this community is distributed using VI Package Manager (VIPM). For more details on VIPM, please read A Note on VI Package Manager

[mi-ni]

Hello,

I would like to use your I2C IP, but we need combined transfer format.

As far as I see, the implementation 1.3.0.1 (distributed via VIPM) does either read or write after the addressing of the slave.

Combined format uses the I2C repeated START condition to combine write and read interaction with a slave (e.g. ADC).

Here you often need to write a configuration for a channel and then read the result after repeated start.

Do you have a version in preparation with support of this feature or can you give a hint, where we can easily change the state machine?

Thank you & greetings

  Michael

[ZY_Ong]

Does anyone have idea what is the missing portion for R Series - NI I2C FPGA Simulation - Host.vi?

[UMASO]

Hi, I had the same situation and below was what I did to make it work.  Hope this helps!

[MattFitz]

The image of the code was beneficial!!  I tried to add an updated version for the NI USB 7856R FPGA.  No attach file option 😞