Channel Emulation IP

[Ryan_V[DE]]

Channel Emulation IP » This IP implements inline, real-time DSP in LabVIEW FPGA to apply arbitrary channel models to RF data. Fading profiles are computed in real-time on the host, and dowloaded to the FPGA where they are interpolated and applied to the data stream.

Description: This IP emulates an over-the-air (OTA) channel for a wireless communication link.  By combining floating point host code and fixed point FPGA code, the channel emulator provides flexible channel profiles and models that can be easily added to and/or modified. It provides two custom channel profiles which are deterministic and stochastic with multiple input multiple output (MIMO) configurations.

Additional Documentation:

• After Installation - C:\Program Files (x86)\National Instruments\LabVIEW 2012\user.lib\_NI Channel Emulation IP\documentation\Real-time MIMO Channel Emulation on the NI PXIe-5644R Vector Signal Transceiver.docx

Compatibility:

• LabVIEW Versions: 2012
• Verified hardware targets: NI PXIe-5644R, NI PXIe-5645R
• Links to relevant examples: Channel Emulation Example for the NI PXIe-5644R

Dependencies:

• none

Performance:

• 1 input I/Q pair per loop iteration / clock cycle for RF input stream(s)
• Up to 2 RF input channels (for 2x2 MIMO)
• 1 input I/Q pair for fading profile stream at 1/8192 input RF stream rate
  
• I/Q pairs as two I16 values concatenated into a U32

FPGA Footprint:

Xilinx Virtex-6 LX195T

• 22.1% / 27553 LUTs
• 14.9% / 37113 Flip-Flops
• 41.9% / 144 Block RAMs
• 46.3% / 296 DSP Slices
• 140 MHz maximum achievable clock rate (empty FPGA)

Latest Version:

• Channel Emulation IP 1.0.0 (LabVIEW 2012)

Previous Versions:

• none available

Note: All source on this community is distributed using VI Package Manager (VIPM). For more details on VIPM, please read A Note on VI Package Manager