Example Code

Switch Debouncer for FPGA Applications with the Spartan-3E Starter Kit or NI Digital Electronics FPGA Board

    Software

  • LabVIEW FPGA Module

Code and Documents

Attachment

 

Introduction

Mechanical switch bounce (or chatter) causes a single press of a button to yield many signal transitions in the sub-millisecond range. The 'Debounce Switch' subVI suppresses switch chatter for pushbuttons and slide switches to yield a clean signal. The debounced output normally tracks the the input on each clock cycle. A transition on the input causes the output to change on the following clock cycle, but further output changes are suppressed until the wait time expires, thereby ignoring the switch chatter transient.The default wait time of 250,000 ticks yields a 5ms delay with a 50-MHz system clock.

subVI_front_panel.png

subVI_block_diagram.png

 

The included application VI demonstrates the 'Debounce Switch' subVI by detecting signal transitions with and without the debouncer.

demo_front_panel.png

demo_block_diagram.png

 

Steps to Complete: Demonstrate 'Debounce Switch'

  1. Download 'Debounce Switch' and Demonstration.zip and extract to a suitable folder
  2. Open Demo -- Debounce Switch.lvproj
  3. Select the target of interest, either the Spartan-3E Starter Kit (Digilent S3EBOARD) or the NI Digital Electronics FPGA Board
  4. Open the Top-Level VIs virtual folder, and then open and run [top_level] Demonstrate 'Debounce Switch'.vi
  5. Select the switch of interest, and then press it one time. The number of detected transitions are displayed, both for the switch signal and its debounced version
  6. Click the Clear transition counters button to reset the counters
  7. Choose Transition Type to detect both low-to-high and high-to-low transitions ("either"), low-to-high transitions only ("false-true"), or high-to-low transitions only ("true-false").

 

Steps to Complete: Using 'Debounce Switch' in your own application

  1. Open your existing LabVIEW project that includes an FPGA target
  2. Right-click on FPGA Target and choose Add File
  3. Select the file Debounce Switch.vi from the .zip distribution
  4. Open your application VI
  5. Select the block diagram, right-click on an open area, choose Select a VI, and then select Debounce Switch.vi
  6. Ensure that the subVI is contained within a single-cycle loop
  7. Place the subVI between the FPGA I/O node and its intended destination

 

 

Additional Notes

  1. This subVI must reside in a single-cycle timed loop to achieve correct behavior,
  2. If placed in a standard while-loop, reduce the "wait" value by at least a factor of four, even more if the while-loop contains a time delay. The loop should not contain any subVI with blocking behavior.
  3. The default wait time of 250,000 cycles (5ms for a 50-MHz system clock) was insufficient for the slide switches on my NI DE board; increasing the value by a factor solves the problem.

 

Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.

Contributors