This project is a modified version of the 10-Tap 8-bit Camera with DRAM shipping example, for the PCIe-1473R-LX110 FPGA CameraLink FrameGrabber. The project has been configured to use the PCIe-1473R with the larger Virtex-5 LX110 FPGA, where the shipping example is configured to use the standard PCIe-1473R with a Virtex-5 LX50 FPGA.
This example demonstrates how to acquire images from a 10-tap, 8-bit, extended configuration, Camera Link camera and display the images on the host. This example supports area scan and line scan cameras for both continuous and finite acquisitions.
This example also demonstrates the use of DRAM as a frame buffer for very high speed acquisitions. Data packing and flow-control are also employed to maximize use of the available DRAM and FIFOs in terms of both memory space and performance.
Additionally, the example demonstrates the serial server, which allows third-party camera configuration utilities to communicate with the camera using the Camera Link serial interface while this VI is running.
Steps to Implement or Execute Code
Download and unzip the attached file.
Install PCIe-1473R-LX110 into computer and attached CameraLink camera to Port 0 and Port 1 of framegrabber.
Open project and compile FPGA VI.
Open 10-Tap 8-bit Camera with DRAM(Host) VI, select FPGA on PCIe-1473R, configure acquisition settings and run the VI.