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Synchronizing Clocks on M-series via DDK

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Hi,

We're in a new development cycle and require the clocks on our M-series cards (6259, 6225) to be synchronized. I have searched the NI docs and the Forums for information but am coming up short on details to implement the sync.

 

First a bit of background... Two cards per computer. The 6259 master samples 24 AI at 2000 S/s using a 49140 Hz Conversion rate and the 6225 slave samples 12 AI at 200 S/s using a 2457 Hz Conversion rate.

 

My understanding of the sync process follows. On the 6259 master, the 10MHz Reference clock is exported via a RTSI line. The 6225 slave imports the 10MHz Reference clock and activates it's PLL. The 6259 AI SampleClock is exported via a second RTSI line and divided down by 10 to trigger AI sampling on the 6225.

 

How is the 10MHz Reference clock accessed in the DDK? How does the PLL get activated in the master and slave? Can the AI SampleClock be divided down directly prior to export or at import on the slave? Or will the division have to take place via one of the GP Counters? Does anyone have sample code?

 

Thanks!

Gord

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Hey Gord,

 

What operating system are you using? Is there a reason why the DAQmx driver cannot be used in your setup?

 

Regards

 

Perry S.

 

Applications Engineer
National Instruments
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Hi Perry,

 

Our OS is QNX4, so DAQmx isn't an option...

 

Gord

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Hi again,

 

We've taken a stab at getting the two card clocks to sync. At this point we are able to measure 10MHz clock pulses on RTSI0, but the card clocks are definitely not in sync. MSC_Clock_Configure has been modified to support sync options of Master/Slave/None and is included as an attachment. Function exportSignal has also been updated to support several other direct route signal sources.

 

 

Are we missing anything in our Master clock configuration? Is there a preferred way of configuring the Master? What needs to be done in the Slave configuration to make it functional? Can function PLL_Status.readPLL_Locked be used to test for sync between the cards or is it telling us something else?

 

Thanks!

Gord

 

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Solution
Accepted by topic author GordS

Just a quick update on this issue.  We were able to help get the application up and running.  The main issue was the PLL_Control register wasn't being written correctly.  That should have been as follows:

 

PLL_Control (454) <== 0x7108

PLL_Multiplier is 8
PLL_Divisor is 1  

PLL_Enable is 1
PLL_VCO_Mode is 3

------
Zach Hindes
NI R&D
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