Detect 0% and 100% PWM Duty Cycles on 660X Card

[schm1347]

Hi,

We essentially want to be able to detect 0% (all low) and 100% (all high) duty signals as well as > 0% and < 100% duty.  However, I noticed that when performing buffered pulse width measurement, if either 0% or 100% duty occurs, the previous detected duty is stored.  It seems as if the next edge or level change isn't detected, then the HWSave or SWSave registers store the last successful count.  Is there some flag on a status register for the NI PCI-6602 card that would indicate whether PWM is continuing to be detected?

Thanks,

Jeff S.

[Tom_W_[DE]]

Hi Jeff-

You might be able to achieve this operation by setting the Counting_Mode to Synchonous_Source mode.  Check out the descriptions for bits 2:0 of the Gi_Counting_Mode register, as described in the 660x RLP manual page 3-22.  In that mode, you also must set the Gi_Alternate_Sync bit as described on page 3-21.

Without making the change to synchronous counting, you might also be able to glean some useful information about when an error condition has been met by periodically monitoring the Gi_Stale_Data bits, as described on page 3-13.

I haven't tested this, but I wanted to offer a few quick tips to try.  Please give these a try and let me know your results.

Thanks-

[schm1347]

Tom -

I checked into your suggestions.  I did not see the stale_data flag change.  However, I did notice that if I started measuring PWM and initially the PWM was at 100% duty, that undocumented bit 14 of G01_status_register started out low.  As soon as PWM was measured (lowering from 100% duty), bit 14 went high.  I'm thinking that I could possibly reset (or something to that effect) the PWM counter after each reading.  That clears bit 14 which remains cleared until the next read cycle if no PWM was detected.  If no PWM is detected, than at that point I could do a quick digital port read (tied to gate input) to determine if PWM is 0% or 100% duty.

However, I am wondering what the purpose of bit 14 as it is not documented?  I'm guessing that it does indeed pertain to G0, because bits 12, 10, 8, 6, 4, 2, and 0 all pertain to G0.

Thanks,

Jeff S.