6225 - how to access 5th ai bank

[ischg]

I'm using the 6225 board with 80 analog input channels (which are structured in 5 banks of 16 analog inputs each). However, I'm unable to address the last bank with channels 64 through 79. There appears to be a 2-bit limitation for the selection of the ai bank, so I'm wondering on how to address the last bank.

I'd really appreciate any pointers.

-Ingmar-

[Nick_F1]

Hi Ingmar,

Thank you for posting on the National Instruments forums.

I am not aware of the limitation that you are speaking of.  Are you using Traditional DAQ or DAQmx?  Is it in LabVIEW that you are seeing this limitation or another program like Signal Express or Measurement and Automation Explorer?  Does it actually say that you can't put in values above 4 or are you just not reading values? 

Are you running in NRSE mode?  If this is the case, then it's possible that you have a manual with an error in it. 
In older revisions of the M-Series Manual it stated:
“In NRSE mode, the reference for each AI <0..15> signal is AI SENSE; the reference for each AI <16..79> signal is AI SENSE 2.”

It should read:
“In NRSE mode, the reference for each AI <0..15> and AI <64..79> signal is AI SENSE; the reference for each AI <16..63> signal is AI SENSE 2.”

Please answer these questions and we can figure out where to go from here.

[ischg]

First of all, thanks for your prompt response. Regarding your questions, I'm using the PCI-6225 in a C++ environment, where I'm accessing the registers directly. So far, I used the register AI_Config_FIFO_Data to specify the input channel. However, this register has a limitation of 4 bits to reference the ai channel number, and 2 bits to reference the ai bank (which is based on the preliminary M Series Register map). However, in this way I can only address the first 4 banks of the board (i.e. up to 64 channels), and thus I cannot use the fifth bank of the PCI-6225.

Is there an alternative way to specify which ai channel I'm reading from? I found the register AI_Config_FIFO_Bypass, but I'm not sure whether I'm on the right track.

Thanks a lot for your help!
-Ingmar-

[Nick_F1]

Hi Ingmar,

I apologize, I didn't realize that you were doing register level programming.  At this point, I will let the people that support this forum take over and help you from here.

[ischg]

I'm still trying to figure out how to access channels 64-79 of my PCI-6225 using register level programming. As indicated before, the dedicated bits in the register AI_Config_FIFO_Data can only address 64 channels, whereas there are 80 channels on the board.

I looked over the register specifications of the M-series again, and to me it is not obvious how to specify inputs from the upper 16 channels.'

I would really appreciate if anyone could give me some pointers on this. Thanks in advance,

-ingmar-

[Tom_W_[DE]]

Hi Ingmar-

In order to get to the upper 16 channels you should select Bank 0.  In addition, you have to set bit 1 of the AI_Config_Gain setting for that channel in the channel config entry.  That bit is not required for the allowed gain settings of the 622x devices (see ai.h from the M Series MHDDK examples for more info), so it won't affect the actual gain setting for the channel.  Beyond this, the settings for channel number are the same as with any other bank, so with those changes you should have access to the upper 16 channels. 

Is it safe to assume you're using the AI channels in RSE mode?  If you're using NRSE mode you'll want to note that the upper 16 channels are actually referenced to AISense on connector 0 and NOT AISense2 on connector 1 as some early documentation might have stated.

Hopefully this helps-

[ischg]

Tom,

I really appreciate your help - it now works like a charm (using differential inputs). Thanks!

-ingmar-

[Tom_W_[DE]]

Hi Ingmar-

Thanks for the feedback- glad to hear it is working for you now.  If you run into anything else please let me know.

[Tom_W_[DE]]

Hi Ingmar-

One more thing I forgot to mention- this method only works for the 6225; other 80-channel M Series variants may require additional settings on a case-by-case basis.  So, if you plan to support those boards additional discussion will be necessary.

Thanks-

[GordonWeast]

Tom,

I want to thank you for providing some very good information here about the register programming interface for these boards.

I've been able to get a driver working for our xPC Target software product.  I added the information from this thread about accessing the upper 16 channels on the 6225 board, but you mentioned that there is a slight variation needed for other 80 channel boards.  It looks to me like that is only the 6255 board.

What is the method I would need to use for that board?

Gordon Weast
xPC Target Development
The MathWorks