I want generate digital pulse at 21.6 KHz (41.6 microsec) using NI 9401, but I try compile my VI (relojes2.vi), i get errors "LabVIEW FPGA: Timing specified in the diagram cannot be met." and the second error is "Error Code: 61056: Component slot_6 does not support crossing clock domains."
I can generate digital pulse with resolution maximum the 41 microsec., but I need 41.6 microsec.
Attached is the a file with the method that executes the above functions if it's of any interest (relojes2.vi)
I use the file "cRIO Train Pulse Gen.vi" for generate pulse at 41 microsec.
Any ideas greatly received
Hardware = cRIO 9002, NI 9401. Software = LabVIEW 8.0 with Module FPGA
Thank's in advanced
Andrès
